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Authors A. Isozaki, T. Yamazato, S. Lu, M. Saito
Title Low-Power Receiver Design with a Noise Enhanced 1-bit ADC and Signal Constellation Rearrangement for 16-QAM Transmitters
Authority IEEE Global Communications Conference (GLOBECOM) , pp.4370-4375
Summary This paper proposes a transmitter that rearranges the 16-QAM constellation for a 1-bit ADC receiver. A 1-bit ADC receiver is more eco-friendly and lower-cost than receivers with a high-resolution ADC. However, in conventional 1-bit ADC receivers, severe degradation of SER (Symbol Error Rate) in high Es/N0 poses a critical problem. This degradation is due to the lack of noise power in high Es/N0, which prevents the receiver from sufficiently benefiting from stochastic resonance. To solve this issue, we propose a novel transmitter that rearranges a 16-QAM constellation based on the probability density function of noise. The rearrangement of constellations mitigates the nonlinearity of a 1-bit ADC, enabling reliable demodulation of multilevel signals in high Es/N0. Numerical examples demonstrate that the proposed transmitter achieves good SER performance across a wide range of Es/N0, even when a 1-bit ADC receiver is employed, compared to conventional transmitters.
年月 2024年12月
DOI/Handle DOI:10.1109/GLOBECOM52923.2024.10901412
開催場所 Capetown, South Africa
研究テーマ 確率共鳴
言語 英語
原稿/プレゼン資料 / (ローカル限定)


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